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dual d-type flip-flop with set and reset; positive-edge trigger

the aip74hc/hct74 are dual positive edge triggered d-type flip-flop. they have individual data (nd), clock (ncp), set (ns()d) and reset (nr()d) inputs, and complementary nq and nq() outputs. data at the nd-input, that meets the set-up and hold time requirements on the low-to-high clock transition, is stored in the flip-flop and appears at the nq output. schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. inputs include clamp diodes. this enables the use of current limiting resistors to interface inputs to voltages in excess of vcc.

  • main features product

  • product documents

  • input levels:

    for aip74hc74: cmos level

    for aip74hct74: ttl level

  • symmetrical output impedance

  • low power dissipation

  • balanced propagation delays

  • specified from -40℃ to 105℃

  • packaging information: dip14/sop14/tssop14

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