the aip74hc/hct191 is an asynchronously presettable 4-bit binary up/down counter. it contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.
asynchronous parallel load capability permits the counter to be preset to any desired value. information present on the parallel data inputs (d0 to d3) is loaded into the counter and appears on the outputs when the parallel load (pl) input is low. this operation overrides the counting function.
counting is inhibited by a high level on the count enable (ce) input. whence is low internal state changes are initiated synchronously by the low-to-high transition of the clock input. the up/down (u/d) input signal determines the direction of counting as indicated in the function table. thece input may go low when the clock is in either state, however, the low-to-highce transition must occur only when the clock is high.
for aip74hc191: cmos level
for aip74hct191: ttl level
synchronous reversible counting
asynchronous parallel load
count enable control for synchronous expansion
single up/down control input
specified from -40℃ to 105℃
packaging information: dip16/sop16/tssop16