the aip74hc/hct280 is a 9-bit parity generator or checker. both even and odd parity outputs are available. the even parity output (pe) is high when an even number of data inputs (i0 to i8) is high. the odd parity output (po) is high when an odd number of data inputs are high. expansion to larger word sizes is accomplished by tying the even outputs (pe) of up to nine parallel devices to the final stage data inputs. inputs include clamp diodes. it enables the use of current limiting resistors to interface inputs to voltages in excess of vcc.
for aip74hc280: cmos level
for aip74hct280: ttl level
word-length easily expanded by cascading
generates either odd or even parity for nine data bits
specified from -40℃ to 105℃
packaging information: dip14/sop14/tssop14