the aip74lvc1g79 provides a single positive-edge triggered d-type flip-flop.
information on the data input is transferred to the q-output on the low-to-high transition of the clock pulse. the d-input must be stable one set-up time prior to the low-to-high clock transition for predictable operation.
inputs can be driven from either 3.3v or 5v devices. this feature allows the use of this device in a mixed 3.3v and 5v environment.
this device is fully specified for partial power-down applications using ioff. the ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.