the aip74lvc2g125 provides a dual non-inverting buffer/line driver with 3-state output. the 3-state output is controlled by the output enable input (pin noe). a high-level at pin noe causes the output to assume a high-impedance off-state.
inputs can be driven from either 3.3v or 5v devices. this feature allows the use of these devices as translators in a mixed 3.3v and 5v environment.
this device is fully specified for partial power-down applications using ioff. the ioff circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
wide supply voltage range from 1.65v to 5.5v
5v tolerant input/output for interfacing with 5v logic
±24ma output drive (vcc=3.0v)
cmos low power consumption
latch-up performance exceeds 250ma
direct interface with ttl levels
inputs accept voltages up to 5v
specified from -40℃ to 105℃
packaging information: tssop8/vssop8