the cd4017 is a 5-stage johnson decade counter with ten spike-free decoded active high outputs (q0 to q9), an active low carry output from the most significant flip-flop (q5-9), active high and active low clock inputs (cp0,cp1) and an overriding asynchronous master reset input (mr).
the counter is advanced by either a low-to-high transition at cp0 whilecp1 is low or a high-to-low transition atcp1 while cp0 is high.
when cascading counters, theq5-9 output, which is low while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the cp0 input of the next counter. a high on mr resets the counter to zero (q0=q5-9=high; q1 to q9=low) independent of the clock inputs (cp0,cp1).
automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.
it operates over a recommended vdd power supply range of 3v to 15v referenced to vss (usually ground). unused inputs must be connected to vdd, vss, or another input.
wide supply voltage range from 3v to 15v
automatic counter correction
tolerant of slow clock rise and fall times
5v, 10v, and 15v parametric ratings
standardized symmetrical output characteristics
specified from -40℃ to 105℃
packaging information: dip16/sop16/tssop16