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cd4027
dual jk flip-flop

the cd4027 is a edge-triggered dual jk flip-flop which features independent set-direct (sd), clear-direct (cd), clock (cp) inputs and outputs (q,q()). data is accepted when cp is low, and transferred to the output on the positive-going edge of the clock. the active high asynchronous clear-direct (cd) and set-direct (sd) inputs are independent and override the j, k, and cp inputs. the outputs are buffered for best system performance. 

it operates over a recommended vdd power supply range of 3v to 15v referenced to vss (usually ground). unused inputs must be connected to vdd, vss, or another input.


  • 主要特点

  • 产品文档

  • wide supply voltage range from 3v to 15v

  • fully static operation

  • 5v, 10v, and 15v parametric ratings

  • standardized symmetrical output characteristics

  • specified from -40℃ to 105℃

  • packaging information: dip16/sop16/tssop16


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