the aip74lvc/lvch16373 are 16-bit d-type transparent latches featuring separate d-type inputs with bus hold (aip74lvch16373 only) for each latch and 3-state outputs for bus-oriented applications. one latch enable (le) input and one output enable are provided for each octal. inputs can be driven from either 3.3v or 5v devices.when disabled, up to 5.5v can be applied to the outputs. these features allow the use of these devices in mixed 3.3v and 5v applications.
the device consists of two sections of eight d-type transparent latches with 3-state true outputs. when le is high, data at the dn inputs enter the latches. in this condition, the latches are transparent, that is, the latch outputs change each time its corresponding d-input changes. the latches store the information that was present at the d-inputs one set-up time (tsu) preceding the high-to-low transition of le. when is low, the contents of the eight latches are available at the outputs. when is high, the outputs go to the high impedance off-state. operation of the input does not affect the state of the latches. bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.
5v tolerant inputs/outputs for interfacing with 5v logic
wide supply voltage range from 1.2v to 3.6v
cmos low power consumption
multibyte flow-through standard pinout architecture
multiple low inductance supply pins for minimum noise and ground bounce
direct interface with ttl levels
all data inputs have bus hold (aip74lvch16373 only)
high-impedance when vcc=0v
specified from -40℃ to 105℃
packaging information: tssop48